TTL SVGA Video Memory

Electric Lunatic

www.ElectricLunatic.net

TTL SVGA

Introduction

Straight away I want to state that although this board generates SVGA video signals, it doesn't offer true 800 x 600 pixel resolution. Each "pixel" this board generates is actually 4 SVGA pixels wide by 3 SVGA pixels high. This is explained later.

This project came about by the need for a VGA board for use in a home built Z80 system. Originally, the Z80 system used a VGA board meant for use with an Arduino and similar devices. This worked well for a number of years but the VGA board eventually stopped functioning. The VGA board originally used (or anything like it) are no longer available. So, I decided to investigate designing and building a VGA board using standard low power Schottky TTL and medium speed static RAM. I wanted the devices used in the design to be readily available and inexpensive.

When I started designing the VGA board, I chose the 800 x 600 resolution because the clock speed that would be used in the circuit was a round figure (40 MHz) that could be easily generated. The problem was that 40 MHz is just marginally in the range of most 74LS devices and definitely too fast for common and inexpensive static RAM.

So, I decided to look around on the internet to see if anyone else has designed and built a VGA board. That's when I found Ben Eater's website. Ben designed and built a circuit that reads an image from a EEPROM (picture of a bird) and generates a video signal for SVGA in 800 x 600 resolution. The circuit was built using 74LS TTL devices. Ben solved the 40 MHz clock rate problem by dividing the number of rendered horizontal pixles by four, requiring a 10 MHz clock rate. This is a simple but brilliant solution and I and I thought "why didn't I think of that?". So Ben Eater's VGA project became the inspiration for my VGA board. I used circuits very similar to (but not a verbatim copy) Ben's circuits for generating the horizontal and vertical synch and blanking signals. A link to Ben Eater's SVGA board project is here : https://www.eater.net/vga

The photographs at the top of this page show the finished VGA board and the text renderd by the board on an SVGA monitor. The host computer is a home built Z80A system. The bottom photograph shows the prototype built on three solderless bread boards. Three solderless bread boards - that was quite a project.

Construction Technique

Ideally this project should have built on a proper PC board. This would have require a four layer board. However, the cost of having a single four layer board of the required complexity was more than I was willing to spend.

So I built the board by hand on perf board. The positive power supply rail was on top and ground at the bottom of the board. I used 14 gauge copper wire, which is used for power outlet wiring in modern domestic and commerical buildings. The power drops to the columns of ICs is copper telephone wiring - the kind used for hard wired telephone systems. The connections between ICs was made with wire wrap wire, soldered to the pins of the IC sockets on the bottom and run in bundles on the top side of the board. This was meticulous and painstaking work, but I did it and it worked.

Overview

This SVGA circuit renders monochrome pixels. Each pixel appears as a small block as each are composed of 4 x 3 SVGA pixels. Despite 200 x 200 resolution, only 192 x 200 can be rendered for reasons explained later. The host CPU can write to video memory but not read from video memory. Video memory can be written only during the vertical blanking period which is 739.2 micro-seconds for 800 x 600 SVGA mode.

Here is a brief description of the block diagram shown above -

Clock

A 10MHz clock is used for timing in this circuit. A 20MHz TTL oscillator can is used and divided down to 10MHz and lower. An oscillator built from inverters and a 20MHz crystal can be used as well. I don't recommend using an RC oscillator as they significantly with temperature and time.

Horizontal Signals Generator

The horizontal synchronization and blanking signals are generated here. The horizontal line clock, (that is one clock pulse per horizontal line) is generated here and sent to the vertical signals generator.

Vertical Signals Generator

The vertical synchronization and blanking signals are generated here. Timing comes from the horizontal line clock that is received from the horizontal signals generator. Signals for when the vertical blanking period begins and ends are also generated and sent to the CPU interface. This informs the host CPU when the vertical blanking period is active so that the CPU can write to the video memory safely.

Video Memory and RGB Signals Generator

The video memory resides here. Each byte in video memory stores 8 horizontal pixels. No color information is stored - the pixel is simply on or off. Each byte in video memory is loaded into a shift register and clock out to the RGB signals at 10 MHz. In this circuit, color is changed using switches to enable each of the RGB signals. Video memory is nothing special, just 150 ns static RAM (6264). The horizontal and vertical synchronization signals are passed through to the monitor.

Host CPU Interface

The SVGA board is accessible by the host CPU using IO writes. An IO address is assigned to the board. A non-maskable interrupt is sent to the CPU when the vertical blanking period begins and ends. The host CPU must keep track of when the vertical blanking period is active. For this reason, the SVGA board is held in reset upon power up until the host CPU is ready to process the non-maskable interrupt. The host CPU must write to video memory only during the vertical blanking period.

SVGA Timing

A timing diagram for 800 x 600 SVGA is shown above.

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